In order to provide integrated circuits (ICs) with increased performance, the characteristic dimensions of devices and spacings on the ICs continue to be decreased. Fabrication of such devices often requires the deposition of dielectric materials into features patterned into layers of material on silicon substrates. In most cases it is important that the dielectric material completely fill such features, which may be as small as 0.01 to 0.05 μm or even smaller in next generation devices. Filling such narrow features, so-called gap filling, places stringent requirements on materials used, for example, for pre-metal dielectric (PMD) or shallow trench isolation (STI) applications. The pre-metal dielectric layer on an integrated circuit isolates structures electrically from metal interconnect layers and isolates them electrically from contaminant mobile ions that degrade electrical performance. PMD layers may require filling narrow gaps having aspect ratios, that is the ratio of depth to width, of five or greater. After deposition, the dielectric materials need to be able to withstand processing steps, such as high temperature anneal, etch, and cleaning steps.
Dielectric materials are commonly deposited by chemical vapor deposition (CVD) or by spin-on processes. Each of these approaches has some limitations for filling very narrow gaps. Plasma enhanced chemical vapor deposition (PECVD) processes provide high deposition rates at comparatively low temperatures (about 400° C.). The main drawback is that PECVD processes have a lower deposition rate inside a gap than at other locations on a surface. The differential deposition rates can create structures overhanging a gap opening, leading to voids within the gap. Typically, for spacings less than 0.25 μm, depending on the aspect ratio, it is difficult to achieve void-free gap fill using standard PECVD approaches.
Phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG) are commonly used for premetal dielectric applications. The films are usually deposited using atmospheric pressure CVD (APCVD), sub-atmospheric pressure CVD (SACVD) or low pressure CVD (LPCVD). Depending on the process conditions and precursors used these methods can achieve an almost conformal coating. Gap-fill is achieved by a post-deposition reflow process in which the material is treated at high temperatures, typically 800-1200° C. The inclusion of phosphorous and boron, in particular, the boron, in the glass lower the glass transition and flow temperatures. However, the use of CVD followed by reflow in future advanced devices will be limited by the high thermal budget required for the reflow process, which is not compatible with certain materials and processes, such as cobalt silicide used at the contact level. For very narrow gaps, less than 0.2 μm, there is an increasing risk that voids may remain, even after high temperature processing.
Some workers have used high density plasma chemical vapor deposition (HDP CVD) to improve gap-fill of PSG and BPSG. In the high density plasma process, deposition and etching occur simultaneously. Etching is most efficient at the top corners of narrow openings, thereby compensating for a lower deposition rate inside the gap. HDP CVD deposition does not require high temperature processing, although an anneal step can be used if a denser film is desired. The HDP CVD process has the drawback that for narrower structures, lower deposition to etch ratios have to be used resulting in a relatively slow overall filling rate. Improved gap-fill may also require modifications in the design of device features, such as rounded corners and sloped sidewalls. Finally, there is also a concern about plasma damage to the device during HDP CVD processing.
Spin-on glasses and spin-on polymers such as silicates, siloxanes, silazanes or silsequioxanes generally have good gap-fill properties. The films of these materials are typically formed by applying a coating solution containing the polymer followed by a bake and thermal cure process. The utility of these spin-on materials may be limited, however, by material shrinkage during thermal processing. Thermal shrinkage is a key consideration for materials which have to withstand high process temperatures, such as materials used for pre-metal dielectric and/or shallow trench isolation applications, which may involve process temperatures exceeding 800° C. High shrinkage can lead to unacceptable film cracking and/or formation of a porous material, particularly inside narrow gaps. Cracked or porous material may have an undesirably high wet etch rate in subsequent process steps.
Thus there remains a need for a dielectric material that provides void-free gap-fill of narrow features at processing temperatures less than the reflow temperatures used currently. The gap-filling materials need to have high thermal stability and reasonable resistance to etching solutions to survive subsequent processing steps.